Electronic circuits comprise layers of semiconductor materials doped with specific elements or combination of elements to make them more or less conductive. It is the predictable and controlled movement of electrons or holes through these semiconductor materials that enable logic to be manipulated in transistors and other integrated devices. Ultimately, electronic circuits in microprocessors and computers are nothing more than multitudes of these integrated logic and storage devices interconnected with each other. These integrated devices are interconnected in electronic circuits with each other using metal layers in horizontal planes above the integrated devices. These metal layers, up to eight or more, are referred to M1, M2, M3, etc. have signal routing and power distribution on them. These metal layers are not necessarily identical to each other. Throughout the metal layers, there is a combination of conductors in which the power distribution supplies bias voltages and ground paths to the integrated devices whereas signal routing supplies signals generated by the devices and transferred to other devices. These power and signal conductors have a minimum spacing which when combined with the minimum allowable conductor width is known as wiring pitch.
Typically integrated devices and electronic circuits are created on the computer using a design space which is nothing more than the set of possible designs and design parameters that meet a specific product requirement. Exploring design space means evaluating the various design options possible with a given technology and optimizing with respect to specific constraints such as power or cost. For a particular semiconductor process technology, such as 0.5 micron CMOS, there are corresponding design rules that state the allowable limits for feature size, feature separation, layer-to-layer overlap, layer-to-layer feature separation, etc. used in the design and layout of integrated circuits. After an integrated circuit has been designed, the design is checked for compliance with the constraints imposed by these design rules, usually by a computerized design rule checker (DRC).
Silicon technology and integrated circuits have evolved to a point where the geometry of transistors and wires are so small with an increase in corresponding circuit density that it is becoming increasingly difficult to manufacture silicon chips with good yield and tolerances. Copper technology is especially sensitive to manufacturing process variations because of its smaller size. The design rules of manufacturers require that all wiring levels on these electronic circuits have a minimum usage requirement, i.e., a minimum density of metal per area, across all portions of the circuit to achieve consistent metal distribution across a wafer to improve manufacturing yield and reliability. For instance, one of these design rules for silicon technology require that all metal levels from M1 to M5 have a minimum density requirement of twenty percent or larger per area of one hundred square microns. The minimum density requirement for the thicker metal levels are ten percent or larger per one hundred square microns area.
FIG. 1 is a layout of conductors, also called buses, of two metal layers of an electronic circuit 10. Metal layer M2 has power distribution and signal routing in which the power distribution comprise ground conductors 210a and 210b, bias voltage conductor 230a, and signal routing 270a, 270b, . . . 270f . . . 270z. Another metal layer M3 lies in a plane above the first metal layer M2 with conductors running perpendicularly to those conductors in metal layer M2. Metal layer M3 shows power distribution comprising ground conductors 310a and 310b and a bias voltage conductor 330a. There may or may not be an intermediate metal layer between metal layers M2 and M3 but it is not shown in FIG. 1. The layout of the power distribution and signal routing of the electronic circuit 10 of FIG. 1 is considered ideal because the ground conductors are equally spaced from the bias voltage conductors and because the signal routing is equally spaced and uniformly interspersed among the power distribution. The conductors of the power distribution are ideally the same size, as are the signal routing albeit a different size than the ground and voltage conductors. When bias voltages are applied to the conductors and when signals are routed through the signal routing, the power and resultant heating will be equally dissipated over the area of the electronic circuit 10 of FIG. 1.
FIG. 2 illustrates a more realistic electronic circuit 20 having two metal layers M2 and M3 positioned one above the other with the power distribution and signal routing as shown in FIG. 1 with the exception that there are fewer signal conductors in metal layer M2. In the M2 layer of FIG. 2, there are only three signal conductors 270c, 270f, and 270z. As can be seen in FIG. 2, there are empty regions 11, 13, 15, 17, and 19 between the power distribution conductors of both the M2 and M3 layers and the signal routing 270c, 270f, and 270z. These empty regions 11, 13, 15, 17, and 19 violate the minimum area usage requirement for metal, especially in sensitive copper technologies as mentioned.
In the electronic circuit 20 of FIG. 2, the design rules and the manufacturing processes require that the empty regions 11, 13, 15, 17, and 19 be filled with metal or other conductors to satisfy a particular minimum usage requirement. In actuality, however, meeting the design rules is not as easy as placing conductors at regular intervals in a metal layer as shown in FIG. 1. Some logic or storage devices are busier than others, some devices require larger operating bias voltages, etc. Thus, in real life, some areas of the electronic circuit are more dense and consume more power and/or generate more signals than other areas of the electronic circuit. These variations of use and power must be considered when meeting minimum usage requirements.
One technique used to fill the areas is the "sprinkle" fill approach undertaken after the chip has been designed but before it is manufactured. The sprinkle fill approach does in fact satisfy the design rules check for minimum area of metal usage but it has several shortcomings. FIG. 3 illustrates the layout of two metal layers M2 and M3 of FIG. 2 but empty regions 11, 13, 15, 17, and 19 and other empty regions have been filled with small floating metal conductors labeled 240a, 240b, 240c . . . 240q in the M2 layer using the sprinkle fill approach. One of the most serious shortcomings is that these metal fills are floating, i.e., they are not electrically connected to either the power distribution or the signal routing. Unexpected line-to-line coupling and vertical coupling between metal planes result from the use of the floating metal fills and causes unpredictable electrical and performance problems. Another problem is that the metal fills 240a . . . 240q are added after the chip design is completed and so are not considered during the normal design process. As any skilled circuit designer is aware, late changes to a design causes problems, such as accidental shorts between signals, and complicates the design and may cause delays if necessary to redesign circuits to correct problems created by the late insertion of these floating metal fills. Yet, another problem is that a large number of spaces have to be filled necessarily increasing the data volume making full chip logical to physical verification (Layout vs. Schematic--LVS) nearly impossible. Because of the checking problems with DRC and comparison of the actual layout of the chip against the schematic transistor design of circuit and interconnections (LVS), many of these electrical problems may not be found before manufacture.
Another such approach to meeting the minimum usage area requirements is given in U.S. Pat. No. 5,272,600 entitled Electrical Interconnect Device with Interwoven Power and Ground Lines and Capacitive Vias to Carey which use capacitive vias in otherwise undedicated areas between overlapping power and ground lines of the various levels to avoid additional conductors.
Thus, there is a need for a electronic circuit design tool to insert fill conductors into a design of an electronic circuit so that the circuit can meet the minimum usage requirement. The placement of the fill conductors must be included early enough in the design of the electronic circuits to undergo DRC/LVS checks and verification. Moreover, there is a need in the industry for the placement of fill conductors in the power distribution and signal routing of integrated circuits. The performance of these fill conductors must be electrically predictable to avoid unanticipated coupling and/or electrical shorting.
These and other objects, features and advantages of the present invention will be further described and more readily apparent from the summary, detailed description and preferred embodiments, the drawing and the claims which follow.